Latches are commonly used to store data in data processing applications. Some latches perform a static latching function, while other latches perform a dynamic latching function. A dynamic latch typically requires less logic circuitry and less time to latch data values than a static latch. Furthermore, because the dynamic latch requires less circuitry than its static counterpart, the dynamic latch also requires less power, less clock loading, and lower internal capacitance. While the dynamic latch provides significant power savings and requires less circuitry than a static latching function, the charge stored in the dynamic latch may dissipate through leakage and the state of the dynamic latch may change after a period of time. An example of a dynamic latch is illustrated in FIG. 1.
In contrast, a state of a value stored in a static latch does not change after a period of time. Static latches typically provide an active feedback path between an output of the latch and an input of the latch that compensates for leakage currents and prevents a state of the latch from changing. The feedback path may be either a constant feedback path or a docked feedback path. An example of a static latch having a constant feedback path is illustrated in FIG. 2. An example of a static feedback latch having a clocked feedback path is illustrated in FIG. 3.
Circuit area and power differences between the two types of static latches are parameters which a designer of a data processing system must evaluate to determine which type of static latch is better suited to a current design. A static latch having a clocked feedback path may be preferred over static latches having a constant feedback path because it provides a faster latch with no contention on internal nodes of the latch. A static latch which has a constant feedback path may consume more power than a clocked feedback latch because of contention on internal nodes of the constant feedback latch when a new value is stored in the latch. The power consumption of the constant feedback latch may be reduced by reducing the size of a the weak feedback device (usually a weak inverter) such the feedback device is just able to store a data value with no leakage and with no unintentional modification of the data value. However, the feedback device is usually weakened by increasing a length of the transistors forming the feedback device. This increased length results in the consumption of more circuit area and may result in increased loading on the internal nodes of the constant feedback latch.
In contrast, a clocked feedback latch performs its feedback function using a feedback device which is not constantly enabled, but which performs its feedback function using an opposite clock phase than that used for the feedforward function. For example, refer to FIG. 3. In FIG. 3, the feedback transistor (16) provides the "out" signal to the input of a latch 14 when the Clock signal is negated. While the clocked feedback latch has less contention than a constant feedback latch, it does require two additional devices two additional transistors to decouple the feedback path while a new value is loaded into the latch. The two additional devices result in increased circuit area and increased power due to the increased loading on the lines providing the Clock signal. Therefore, the merits of the clocked feedback latch over the constant feedback latch must balance the power and area consumed by the weak feedback devices of the constant feedback latches and the power and area consumed by the feedback gating devices of the clocked feedback latch.
Neither the dynamic latch or static latch implementations described herein provide an effective low power implementation of a latch function which may store a data value indefinitely. Each implementation described above has advantages and disadvantages which must be weighed by a designer to determine the implementation that may be implemented with the least adverse effect on the overall data processing system.